Prevalent products in the industry today can only support 8 to 12 OC192 ports, and they suffer from the other limitations mentioned above.
To endeavor to meet some of the quality of service requirements concurrently with data “speed” and “feed” requirements, the prior art has most commonly taken the before-described input buffering approach, wherein the input data is locally buffered on an input port that has no “knowledge” of what input data may also be present at other input ports and contending for the same output port destination. The input port merely blindly makes the request of the input buffered switch to direct its data to the particular output port; and this prior architecture thus has had to live with its classic problems of potential head-of-the-line (HOL) blocking and inability to guarantee delay and jitter in quality of service. The input-buffered systems, accordingly, have to put up with sometimes even unrealistic periods of time before data can make its way to the switch for enabling transmission to destination output ports.
The particular output-buffered approach of the invention, on the other hand, uses a central shared memory architecture comprised of a plurality of similar successive data memory channels defining a memory space, with fixed limited times of data distribution from the input ports successively into the successive memory cells of the successive memory channels, and in striped fashion across the memory space. This enables non-blocking shared memory output-buffered data switching, with the data stored across the memory channels uniformly. By so limiting the time of storing data from an input port in each successive memory channel, the problem is admirably solved of guaranteeing that data is written into memory in a non-blocking fashion across the memory space with bounded delay.